Reconfigurable (programmable or writable) semiconductor devices (also referred to as “reconfigurable devices”) such as field-programmable gate arrays (FPGAs) are widely used due to their flexibility from being rewritable (Patent Document 1, for example).
Typical island-style FPGAs are constituted of logic element CLBs (configurable logic blocks), switching elements SB and CB, and input/output element IOBs.
Logic element CLBs are programmable elements that realize a combinational logic, and each CLB is constituted of a data flip-flop (DFF), a lookup table (LUT), or the like. LUTs having k inputs (k-LUTs) have 2k SRAM (static random access memory) cells, and realize a function with k as the variable. There is a method, for example, in which a truth table of an appropriate logic function is stored in the SRAM, and output is performed on the basis of input with reference to the truth table.
In order to generate a signal path between CLBs to link the logic function portions, switching elements CB and SB, which can switch the signal path are disposed between the CLBs. The switching element CB is an element set between the logic block LB and a wiring channel, and the switching element SB is an element that performs settings between vertical and horizontal wiring lines in portions where the vertical and horizontal wiring lines intersect.
The input/output element IOB is a configuration element that functions as an interface between the input/output and the logic element LB of the device.
The applicant or inventor has developed “memory-based programmable logic devices (MPLD)” (registered trademark) in which a circuit configuration is constituted of memory cell units. MPLDs are disclosed in Patent Document 1 below, for example. In MPLDs, memory arrays referred to as “multi-look-up-tables” (MLUTs) are connected to each other. MLUTs store truth table data and form wiring elements and logic elements. MPLDs realize almost the same functions as FPGAs by having these MLUTs arranged in an array and connected to each other. Also, MPLDs are devices having flexibility for logic regions and wiring regions by using MLUTs both as logic elements and wiring elements by truth table data (Patent Document 2, for example), and differ from FPGAs having specialized switching circuits at the connections between memory cell units.
The optimal arrangement and wiring methods of FPGAs are already under consideration (Patent Document 3). In the case of MPLD logic configuration, the MLUTs operate as logic elements and/or connective elements, and thus, the writing of truth table data to the MLUTs signifies the arrangement of logic operations and/or the wiring between MLUTs. Thus, the generation of truth table data for writing to the MLUTs corresponds to the “arrangement/wiring” of the MPLDs.
The logic configuration of MPLDs is disclosed (Patent Document 4, FIG. 43). However, the disclosure is limited to a general configuration in which the number of input/output units of the MLUT is made to be less than the number of AD pairs (a pair including an address line and a data line, the pair connecting MLUTs to each other).